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NJW4351 - 1 - ?ver.2010-03-26 NJW4351vc3 NJW4351d unipolar stepper motor driver general description package outline the NJW4351 is a high efficiency dmos unipolar stepper motor driver ic. compared to previous devices, it is more suitable for low voltage operation, capable of handling 5.0v, 3.3v and the like logic circuits. drive stage consists of dmos which produces high efficiency and low heat generation motor drive circuit. the motor can be controlled by the step and dir system. further more, to improve controlla bility of system, mo, enable, reset and pd function are included, various applications are possible. features ? supply voltage v dd =2.7 to 5.5v v mm = to 55v ? output current io=1.5a peak at v dd =5v ? low quiescent current i dd =500 a typ. ? step&dir input operation (internal translator) ? half/full mode generation ? ttl compatible input with schmitt-comparator ? enable function ? reset function ? mo (motor origin monitor) -position-indication output ? pd (standby) function ? under voltage lock out ? thermal shutdown circuit ? alarm output function (as the protection circuit operates) ? bcd technology ? package outline ssop20-c3, dip16 block diagram NJW4351 out2b out2a out1b out1a sense1 enable mo gnd vdd sense2 under voltage lock out thermal shut dow n alarm translator pd power on reset bias circuit gate drive di r reset hsm step
NJW4351 - 2 - ver.2010-03-26 pin connection ssop20-c3 dip16 pin function list pin# ssop20-c3 dip16 terminal name function remark 1 16 pd power saving state setting input terminal l=standby, h=normal operation 2 1 vdd logic voltage supply terminal logic voltage supply 3 2 hsm half/full step mode setting input terminal l=full, h=half 4 3 step stepping pulse input terminal the translator is triggered by positive edge of step pulse. 5 4 dir direction setting input termi nal l=forward, h=reverse 6 5 reset reset input terminal l=the translato r is initialized, h=normal operation 7 6 enable phase output off input terminal l=active, h=normal operation 8 7 mo mo output terminal when the translator is in initial status, l level is to output. 9 8 alarm internal protection operation detection output terminal when the internal protection oper ation is detected, l level is to output. 10 9 gnd logic ground terminal logic ground 11,12,19,20 - n.c. no connection no connection 13 10 out2a 2ch output terminal a ? 14 11 sense2 current detection resistance connection terminal 2 it connects resistance for the detection of the side of 2ch. at the unused time, it connects with gnd. 15 12 out2b 2ch output terminal b ? 16 13 out1b 1ch output terminal b ? 17 14 sense1 current detection resistance connection terminal 1 it connects resistance for the detection of the side of 1ch. at the unused time, it connects with gnd. 18 15 out1a 1ch output terminal a ? sense1 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 p d vd d hsm ste p di r rese t enable m o alarm gn d n.c. n.c. out1a out1b out2b sense2 out2a n.c. n.c. 1 8 2 3 4 5 6 7 1 6 9 1 5 1 4 1 3 12 11 1 0 vd d hsm step di r rese t enable m o alarm pd out1a out1b sense1 out2b sense2 out2a gnd
NJW4351 - 3 - absolute maximum ratings (ta=25 c) (*1): mounted on glass epoxy board based on eia/je dec. (114.3x76.2x1.6mm: 2layers/4layers) recommended operating conditions (ta=25 c) parameter symbol test condition min. typ. max. unit logic supply voltage v dd 2.7 3.3 5.5 v v dd =5v - 500 - ma output current io v dd =3.3v - - 500 ma parameter symbol ratings unit logic supply voltage v dd 7 v vdd pin motor output voltage v o 55 v out1a/1b/2a/2b pin logic input voltage v in 7 v step, dir, hsm, reset, enable, pd pin alarm output voltage v alarm 7 v alarm pin mo output voltage v mo 7 v mo pin output current io 1.5 a out1a/1b/2a/2b pin alarm output current i alarm 20 ma alarm pin mo output current i mo 20 ma mo pin operating temperature topr -40 to +85 c - junction temperature tj -40 to +150 c - storage temperature tstg -50 to +150 c - 1.0 w (*1) mounted on 2layers pcb power dissipation (ssop20-c3) p d 1.5 w (*1) mounted on 4layers pcb 1.2 w device itself 1.4 w (*1) mounted on 2layers pcb power dissipation (dip16) p d 2.0 w (*1) mounted on 4layers pcb
NJW4351 - 4 - ver.2010-03-26 electrical characteristics ( v mm =24v, v dd =pd=3.3v, r l =1k ? , r mo =3.3k ? , r alarm =3.3k ? , ta=25 c ) parameter symbol test condition min. typ. max. unit general quiescent current i dd step,dir,hsm,reset,enable=3.3v, except i ih - 0.5 0.8 ma quiescent current (standby) i pd pd=0v, except i ih - - 1.0 ua input block1 (step) h level input voltage1 v ih1 2.0 - - v l level input voltage1 v il1 0 - 0.8 v input hysteresis voltage1 v ihys1 0.4 0.55 - v h level input voltage2 v ih2 v dd =5v 2.4 - - v l level input voltage2 v il2 v dd =5v 0 - 0.8 v input hysteresis voltage2 v ihys2 v dd =5v 0.4 0.55 - v h level input current i ih step=3.3v 15 33 45 ua l level input current i il step=0v - 10 20 ua input pull down resistance r down - 100 - k ? input pulse widths tp 2 - - us input block2 (pd/dir/hsm/reset/enable) h level input voltage1 v ih1 2.0 - - v l level input voltage1 v il1 0 - 0.8 v input hysteresis voltage1 v ihys1 - 0.13 - v h level input voltage2 v ih2 v dd =5v 2.4 - - v l level input voltage2 v il2 v dd =5v 0 - 0.8 v input hysteresis voltage2 v ihys2 v dd =5v - 0.14 - v h level input current i ih pd, dir, hsm, reset, enable=3.3v, per input 15 33 45 ua l level input current i il pd, dir, hsm, reset, enable=0v, per input -200 0 +200 na input pull down resistance r down - 100 - k ? input pulse widths tp 2 - - us data setup time t ds 1 - - us data hold time t dh 1 - - us motor output block (out1a/out1b/out2a/out2b) output on resistance1 r o1 io=500ma - 1.2 1.45 ? output on resistance2 r o2 v dd =5.0v, io=500ma - 0.9 1.25 ? output leak current i oleak enable=0v,vo=50v - 1 5 ua delay time t delay at turn on - 0.3 - us sense terminal leak current i senseleak enable=0v, v sense =1v(sense gnd) - - 1 ua mo output (mo) l level output voltage v mo i mo =10ma - 0.3 0.5 v mo terminal leak current i moleak v mo =5.5v - - 1 ua mo output (alarm) l level output voltage v alarm i alarm =10ma - 0.3 0.5 v alarm terminal leak current i alarmleak v alarm =5.5v - - 1 ua thermal shutdown block thermal shutdown operating temperature t tsd1 - 170 - c thermal shutdown recovery temperature t tsd2 - 140 - c thermal shutdown hysteresis ? t tsd - 30 - c under voltage lock out block uvlo operating voltage v uvlo1 1.6 1.9 2.2 v uvlo recovery voltage v uvlo2 1.9 2.2 2.5 v uvlo hysteresis voltage ? v uvlo 0.2 0.3 0.4 v
NJW4351 - 5 - pin/ circuit operational definition ? logic input pins operational voltage definition ? logic input pins timing definition 0 v v 0.8 v 5.0 v 2.0 v ? v hys a t vdd=3.3v l level h level l lebvel h level l level l level input voltage h level input voltage 0 v v i n v dd 2.0 v 0.8 v h level input voltage l level input voltage at vdd=3.3v master pin step v v ih =2.0v v il =0.8v slave pins v ih =2.0v v il =0.8v t t ds2 t dh1 reset, pd data setup time and data hold time are defined to positive edge of step. t ds1 ,t ds2 =data setup time, t dh1 ,t dh2 =data hold time t ds1 ,t dh1 =hsm,dir,reset, pd, t ds2 ,t dh2 =hsm,dir t ds1 t dh2 tp tp hsm, dir tp tp
NJW4351 - 6 - ver.2010-03-26 ? thermal shutdown operational definition ? under voltage protection operational definition 170c 150c (tj max) tsd operating temp (output suspention) tsd recovery temp (normal operation) -40c tj 140c hysteresis temp 5.5 v 1.9 v 2.1 v uvlo operating voltage(output suspention) uvlo recovery voltage(normal operation) hysteresis voltage 0 v vdd 2.7 v recommended operating maximum voltage recommended operating minimum voltage
NJW4351 - 7 - terminal status step function mo function negative edge - h the translator is in noninitial status positive edge internal translator gose on ever y this ed g e l the translator is in initial status open - hsm function alarm function h half step h normal operation l full step open full step ( inside pull down ) dir function h reverse lforward open forward ( inside pull down ) enable function hactive l out terminals are off , but internal lo g ic circuit is on. open out terminals are off , but internal logic circuit is on. ( inside pull down ) reset function hactive l reset open reset (inside pull down) pd function hactive l reset+power saving open reset+power saving ( inside pull down ) mo-motor origin position output alarm-alarm output step-motor stepping pulse input dir-direction command input l out terminals are off, as the protection circuit operates. enable-enable input reset-reset input pd-power down state input hsm-half/full step mode input
NJW4351 - 8 - ver.2010-03-26 timing chart step after por 1 2 3 4 5 6 7 8 out2b off off on on on off off off off out2a on off off off off off on on on out1b off off off off on on on off off out1a on on on off off off off off on mo on off off off off off off off on step after por 1 2 3 4 5 6 7 8 out2b off off off off on on on off off out2a on on on off off off off off on out1b off off on on on off off off off out1a on off off off off off on on on mo on off off off off off off off on fig.1 full step mode / forward direction sequence fig.2 full step mode / reverse direction sequence fig.3 half step mode / forward direction sequence fig.4 half step mode / reverse direction sequence out2b out2a out1b out1a por reset h dir enable hsm step 12341234 1 l h l l off on off on mo on out2b out2a out1b out1a enable por reset h dir hsm step 12341234 1 h h l l off on off on mo on out2b out2a out1b out1a por reset h dir enable hsm step 12345678 1 l h h l off on off on mo on out2b out2a out1b out1a por reset h dir enable hsm step 12345678 1 h h h l off on off on mo on step after por 1 2 3 4 out2b off off on on off out2a on on off off on out1b off on on off off out1a on off off on on mo on off off off on step after por 1 2 3 4 out2b off on on off off out2a on off off on on out1b off off on on off out1a on on off off on mo on off off off on
NJW4351 - 9 - * when enable is active out terminals are off, but internal logic circuit is on. fig.5 full step mode / enable sequence fig.6 half step mode / enable sequence fig.7 full step mode / reset sequence fig.8 half step mode / rest sequence * when enable is active out terminals are off, but internal logic circuit is on. * when reset is active out terminals are off, and internal logic circuit is to reset. out2b out2a out1b out1a por reset h dir enable hsm step 12341234 1 l h l l off on off on mo on out2b out2a out1b out1a por reset h dir enable hsm step 12345678 1 l h h l off on off on mo on out2b out2a out1b out1a por reset h dir enable hsm step 12* * *123 4 l h l l off on off on mo on out2b out2a out1b out1a por reset h dir enable hsm step 12 123 4 l h h l off on off on mo on *** * when reset is active out terminals are off, and internal logic circuit is to reset.
NJW4351 - 10 - ver.2010-03-26 pd out2b out2a out1b out1a por reset h dir enable hsm step 12* * *123 4 l h l l off on off on mo on h pd out2b out2a out1b out1a por reset h dir enable hsm step 12 123 4 l h h l off on off on mo on *** h fig.9 full step mode / pd sequence * when pd is active it fo rces all settings to initializ e and be in stand-by mode, and mo is to be low. fig.10 full step mode / pd sequence * when pd is active it fo rces all settings to initializ e and be in stand-by mode, and mo is to be low.
NJW4351 - 11 - function description the NJW4351 is designed for a high-performance constant-voltage unipolar stepper motor. using a general-purpose step&dir moti on controller, the device can ea sily control a stepper motor when combined with a pulse generator. the maximum value of the phase output is 55 v that keeps the voltage margin of the motor from exceeding the limit, which is a common problem with uni polar winding systems. it simplifies the design of power control circuits during phase turn-off. logic input block all inputs are ls-ttl compatible. input block1 (step) has schmitt comparator to keep the thresh voltage unchanged even if logic supply voltage applied to it varies. it produces hesteresis voltage for noise immunity. input block2 (pd, dir, hsm, reset, enable) has schmitt inverter for the main pu rpose of noise immunity. inputs are internally connected to gnd by pull-down resist ances, being open, the device recognizes to be low. ? step ? stepping pulse the translator starts counting on every positive edge of the step. in full step mode, the pulse turns the stepper motor at the basic step angle. in half step mode, two pulses are required to turn the motor at the basic step angle. the dir (direction) signal and hsm (half/full mode) are latched to the step positive edge and must therefore be established before the start of the positive edge. ? dir ? direction the dir signal determines the step direction. the direction of the stepper motor depends on how the NJW4351 is connected to the motor. dir can be modified anytime, it miss-steps when it is simultaneous with the positive edge. ? hsm ? half/full step mode switching this signal determines whether the stepper motor runs at half step or full step mode. the translator is set to half step mode when hsm is low. like dir, hsm can be modified anytime but not when its simultaneous with the positive edge. ? enable ? phase output off all phase outputs are turned off when enable goes high reducing power consumption. ? reset a two-phase stepper motor repeats the same winding energizing sequence every angle that is a multiple of four of the basic step. the translator is repeated every four pulses in full step mode and every eight pulses in half step mode. when reset is low, the translator is initialized and the phase outputs turn-off. when returning to high, the phase outputs are set to the initial energizing pattern output status. ? pd-power down when pd goes low, it forces all settings to initialize and be in stand-by mode. and mo is to be low.
NJW4351 - 12 - ver.2010-03-26 por ? power on and reset function the por connected to vdd is to prevent miss-step under unstable condition of the inputting of logic supply voltage vdd. after inputting vdd, the phase outputs are set to the initial energizing pattern output status. phase output block the phase output block consists of four open-drain dmos fet capable of sinking max 1.5a. mo ? motor origin monitor in initialized position of the translator, mo output low to in dicate to external devices t hat it is the initial energizing pattern output status.
NJW4351 - 13 - precautions 1. never disconnect the device or pc-board when power is supplied. 2. remember that excessive voltages might be generat ed by motor, even though clamping diodes are used. 3. choose a motor that is proportional to the current y ou need to establish desired torque. a high supply voltage will gain better stepping performance. if the motor is not specified for the vmm voltage, a current limiting resistor will be necessary to connect in series with center tap. this changes the l/r time constant. 4. avoid vmm and vdd power supplies with serial diodes (without filter capacitor) and common ground with vdd. 5. to change actual motor rotation direction, exchange motor connections at out1a and out1b (out2a and out2b). 6. half-stepping in the half-step mode, the power input to the motor alternates between one or two phase windings. in half-step mode, motor resonances are reduced. in a two-phase motor, the electrical phase shift between the windings is 90 degrees. the torque developed is the vector sum of two windings energized. therefore, when only one winding is energized, which is the case in half-step mode for every second step, the torque of the motor is reduced by approximately 30%. this causes a torque ripple. 7. drive circuits high-performance stepper motor operation requires windings to be energized immediately at phase turn-on and quickly turned off when not in use. 8. phase turn-off considerations when the winding current is turned off, induced high voltage spike will damage the drive circuits if not properly suppressed. refer to the turn-off circuits described in figures 11 to 14. the voltage potential at the phase output terminal may sometimes become negative (gnd or below) due to the configuration of the turn-off circuit or the kickback voltage generated in it. in this condition there is a danger of a malfunction occurring in the logic circuit inside the device. 8.1. precautions against high voltage using the zener-diode turn-off circuit refer the zener-diode turn-off circuit (see fig.15). zener-diode voltage value is vz and the forward voltage of the diodes connected in series with the zener-diode is vd, the voltage vp of the phase output (out1a, out1b, out2a, out2b) terminal when the turn-off oper ation have occurred is expressed by the following equation. vp = vmm ? (vz + vd) the higher voltage, vz, used, the shorter is the turn-off time of the winding current, thus producing high speed operation of the stepper motor. note, however, that depending on the zener voltage, vz, the voltage potential at the phase output terminal may become negativ e, so design the turn-off circuit as indicated below. 8.1.1. when vp is a positive voltage: vmm > vz + vd the circuit configuration is that of fig.15. set the zener voltage. for example, if vmm is 12 v, vz + vd is no higher than12v. 8.1.2 when vp is a negative voltage: vmm < vz + vd the circuit configuration is that of fig.16. in order to prevent a malfunction due to a negative voltage, be sure to insert diodes in series with the phase output terminals.
NJW4351 - 14 - ver.2010-03-26 i vmm fig.11 diode and turn off circuit. i r vmm fig12 resistor and turn off circuit. vz i vmm fig.13 zener diode and turn off circuit. i vmm v z fig.14 power regeneration and turn off circuit. vmm v z fig.15 zener diode and turn off circuit 2. vd turn off circuit (case of zener diode) vmm v z turn off circuit (case of zener diode) negative voltage prevention diode fig.16 turn off negative voltage prevention circuit by zener diode
NJW4351 - 15 - application circuit vmm micro controller/ microprocessor + vdd + outpu t outpu t outpu t outpu t outpu t inpu t outpu t inpu t r mo r al ar m NJW4351 out2b out2a out1b out1a sense1 enable mo gnd vdd sense2 under voltage lock out thermal shut dow n alarm translator pd power on reset bias circuit gate drive di r reset hsm step
NJW4351 - 16 - ver.2010-03-26 typical characteristics idd - vdd step=hsm=dir=reset=enable=pd=vdd, ta=25 o c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 vdd [v] idd [ma] ron - vdd io=500ma, ta=25 o c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 01234567 vdd [v] ron [ ? ] ron1 - io vdd=3.3v, ta=25 o c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 100 200 300 400 500 io [ma] ron1 [ ? ] ron2 - io vdd=5.0v, ta=25 o c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 250 500 750 1000 1250 1500 io [ma] ron2 [ ? ] pd - io vdd=3.3v,ta=25 o c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 100 200 300 400 500 io [ma] pd [w] two channels on one channel on pd - io vdd=5.0v,ta=25 o c 0 1 2 3 4 5 6 7 8 9 0 250 500 750 1000 1250 1500 io [ma] pd [w] two channels on one channel on
NJW4351 - 17 - typical characteristics vor - io vdd=3.3v, enable=0v,ta=25 o c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 250 500 750 1000 1250 1500 io [ma] vor [v] vmo - imo vdd=3.3v, reset=0v,ta=25 o c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 5 10 15 20 imo [ma] vmo [v] ron1 - tj vdd=3.3v, io=500ma 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 -50 -25 0 25 50 75 100 125 150 tj [deg.c] ron1 [ ? ] ron2 - tj vdd=5.0v, io=500ma 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 -50 -25 0 25 50 75 100 125 150 tj [deg.c] ron2 [ ? ] idd1 - tj vdd=3.3v 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -50 -25 0 25 50 75 100 125 150 tj [deg.c] idd1 [ma] vor - tj vdd=3.3v,io=500ma 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 -50 -25 0 25 50 75 100 125 150 tj [deg.c] vor [v]
NJW4351 - 18 - ver.2010-03-26 typical characteristics [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. vmo - tj vdd=3.3v,imo=10ma 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -50 -25 0 25 50 75 100 125 150 tj [deg.c] vmo [v]

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